1. Field of the Invention
The present invention relates to a semiconductor device with a self-aligned contact and a method for manufacturing the semiconductor device with a self-aligned contact.
In the technical field of semiconductor devices, it is common and necessary to contact doped regions that are disposed in a semiconductor substrate. When two neighboring word lines are disposed on a surface of the semiconductor substrate and a doped region is disposed in the semiconductor substrate between the two neighboring word lines, it is known to encapsulate the word lines on their tops and side walls with a so-called liner as an etch resistant material to gain a self-aligned contact between the two word lines to the doped region.
The encapsulation for the word lines typically are formed of silicon nitride, the word lines typically are formed of doped poly silicon and an insulating layer covering the word lines and the substrate typically are formed of a silicon oxide.
The etch selectivity between the silicon oxide and the silicon nitride is nowadays not sufficient for modern semiconductor devices. While etching the insulating layer formed of silicon oxide with a roughly patterned resist mask, the encapsulation of the word lines directs the etching process self-aligned to the doped region between the neighboring word lines. During the process, the encapsulation of the word lines is etched as well and holes can be etched into the encapsulation resulting in damage to the word line or a short-circuit between the word line and the contact plug filled in between the two neighboring word lines for contacting the doped region in the substrate.
U.S. Pat. No. 5,792,703 describes a liner containing aluminum oxide as an etch mask for a gate stack.
U.S. Pat. No. 5,384,287 shows an additional silicon oxide layer between the poly silicon gate stack and the aluminum oxide liner.
2. Summary of the Invention
It is accordingly an object of the invention to provide a semiconductor device with a self-aligned contact and a method for manufacturing the device which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, which prevents short circuits between neighboring conductors and reduces capacitive coupling between neighboring conductors.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor device. The device contains a substrate having a surface and a first conductor disposed on the surface of the substrate. The first conductor has a first top surface and a first side wall. A second conductor is disposed on the surface of the substrate. The second conductor has a second top surface and a second side wall, and the first conductor and the second conductor are disposed next to each other. A first encapsulation is disposed on the first top surface and on the first side wall of the first conductor. A second encapsulation is disposed on the second top surface and on the second side wall of the second conductor. The first encapsulation or the second encapsulation contains titanium oxide, boron nitride, silicon carbide, magnesium oxide, carbon in a diamond like structure, or carbon in an amorphous structure.
The invented semiconductor device contains an encapsulation for a conductor. The encapsulation contains titanium oxide, boron nitride, silicon carbide, magnesium oxide, carbon in a diamond like structure, or carbon in an amorphous structure. The mentioned materials have the advantage of a high etch selectivity compared to silicon oxide. This enables a self-aligned contact with the encapsulation as a self-aligning etch mask. Due to the high etch selectivity between the mentioned materials and silicon oxide, the encapsulation, namely the liner, can be built thinner while still providing the same etch resistivity as materials known from the prior art. The thinner liner enables the first conductor, the second conductor, or the contact plug between the first and the second conductor to be built with a larger cross-section area resulting in a lower resistance.
Another advantage of the invention is that a malfunction of the semiconductor device due to a short circuit between the first conductor or the second conductor with the contact plug can be avoided due to the improved etch resistivity of the new liner materials.
According to an embodiment of the present invention a third encapsulation is disposed on the first top surface and on the first side wall of the first conductor between the first conductor and the first encapsulation. The third encapsulation is disposed between the first conductor and the first encapsulation. The third encapsulation enables another material with a different dielectric constant to be disposed between the first conductor and a contact plug.
According to another embodiment of the present invention the first encapsulation contains a first dielectric constant and the third encapsulation contains a second dielectric constant, whereby the second dielectric constant is less then the first dielectric constant. This reduces the capacitive coupling between the first conductor and a contact plug.
In a further embodiment of the present invention the third encapsulation contains silicon oxide. Silicon oxide provides a dielectric constant of approximately 3.9, which can be used to reduce the capacitive coupling between the first conductor and the contact plug. In a preferred embodiment of the present invention, a contact plug is disposed on the surface of the semiconductor substrate between the first conductor and the second conductor. The contact plug is capable of electrically contacting a doped region in the substrate, which is disposed between the first conductor and the second conductor while maintaining the isolation between the first conductor, the second conductor and the contact plug.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for manufacturing a semiconductor device with a self-aligned contact. The method includes providing a semiconductor substrate having a surface and forming a first conductor on the surface of the substrate. The first conductor has a first top surface and a first side wall. A second conductor is formed on the surface of the substrate, the second conductor has a second top surface and a second side wall. A first encapsulation is disposed on the first top surface and on the first side wall of the first conductor. A second encapsulation is disposed on the second top surface and on the second side wall of the second conductor. The first encapsulation or the second encapsulation contains titanium oxide, boron nitride, silicon carbide, magnesium oxide, carbon in a diamond like structure, or carbon in an amorphous structure.
According to an embodiment of the present invention the first conductor and the second conductor are disposed on the surface of the semiconductor before the first encapsulation and the second encapsulation are disposed on the conductors.
A further embodiment of the present invention contains the step of etching a contact hole between the first conductor and the second conductor using the first encapsulation and the second encapsulation as a self-aligning etch mask. The contact hole is etched for receiving a contact plug. The self-aligning of the contact hole is enabled by the first encapsulation and the second encapsulation that direct the etching processxe2x80x94for etching the contact holexe2x80x94between the first conductor and the second conductor towards the surface of the semiconductor. The first conductor and the second conductor are covered by the first encapsulation and the second encapsulation so that they are not etched.
In a further embodiment of the invention the step of filling the contact hole with a contact plug between the first conductor and the second conductor is performed. The contact plug is a self-aligned contact plug between the first conductor and the second conductor and contacts a doped region that is disposed between the first conductor and the second conductor in the substrate.
Another embodiment of the invention contains the step of disposing a third encapsulation on the first top surface and on the first side wall of the first conductor before the first encapsulation is disposed on the first conductor. This process step builds a third encapsulation between the first conductor and the first encapsulation. The third encapsulation can advantageously contain a material with a low dielectric constant near 1. For example silicon oxide is suitable as a material for the third encapsulation providing a dielectric constant of roughly 3.9.
According to another embodiment of the invention the first encapsulation is deposited as a titanium layer and is oxidized in an oxygen-containing atmosphere to titanium oxide. This enables a process step for depositing a titanium layer, which is oxidized afterwards. Also a process step for depositing the first encapsulation or the second encapsulation or the third encapsulation with the desired stoichiometry is suitable to manufacture the inventive configuration.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor device with a self-aligned contact and a method for manufacturing the device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.